The era of AI means that most applications now require Heterogeneous architectures using: multi-CPU clusters using L1, L2 and L3 caches, and often with more than 1 CPU architecture, combining ARM and RISC-V subsystems; 2D arrays of GPUs; and multiple AI accelerators.

These are often built as chiplets, which are combined into 2.5D and 3D systems using UCIe/PCIe, external 3D stacked memories. Such systems require state-of-the-art design and verification methodologies, including emulation.

Agenda (CEST)

Time Details

     12.00           Arrival, registration, networking, light refreshments

     13:00           SIP Verification Challenges
                          by Andrew Bond, Axelera AI

      13:30          In-house tool development for offline debugging
                          by Jerome Sauger, Axelera AI

      14:00         Agentic Control Framework: Architecting the Future
                         of Autonomous Design Verification Systems
                         by Abhilash Chadhar, Axelera AI
 

      14:30          Hardware Emulation for HW-SW Co-Verification
                          of Heterogeneous SoCs
                          by Kareem Ab, Synopsys
 

      15:00          Break with refreshments/networking

      15:30          Design & Verification of Heterogeneous Systems
                          by Jebaselvi Johnson, PrimeSoc Technologies

      16:00          NoC automation prevents sub-optimal implementations
                          that DV tools won’t catch by Rick Bye, Arteris
 

      16:30          Speaker 7 - TBA
 

      17:00          Refreshments & Pizza/networking